1. Field
This disclosure relates generally to electrical protection, and more particularly to electrical protection for an integrated circuit.
2. Related Art
An integrated circuit (IC) die may be subject to an overstress event such as a high-voltage event that can be destructive to the IC. An electrostatic discharge (ESD) event is such an overstress event that can occur during a manufacturing process, assembly, testing, or in the system application. Some on-chip ESD protection networks use an active MOSFET (Metal Oxide Semiconductor Field-Effect Transistor) rail clamp protection scheme with large ESD diodes between features being protected from ESD, such as input/output (I/O) pads, and the power supply rails. This approach has been effective but the currents involved can be large enough so that the MOSFET must accordingly be large, which is accomplished by using many MOSFET transistors in parallel, referred to as fingers. The number of MOSFET transistor fingers used to implement a MOSFET at an ESD protection device can be large enough so that the transistor fingers are divided into segments that are separated from one another by well-ties to ensure compliance with design rules that specify a maximum distance between any point of a transistor source/drain region and a well-tie such as to improve the intrinsic latch-up robustness of the MOSFET as well as its latch-up robustness with respect to any other nearby integrated circuit components.
FIG. 1 illustrates an overhead view of a portion 9 of a layout of an integrated circuit die having an ESD protection circuit comprising a MOSFET implemented using a plurality of MOSFET fingers 41 connected in parallel. The illustrated portion 9 includes a well-tie structure that includes a well-tie 21 and an adjacent dielectric region 11. The well-tie 21 includes a ring portion 90 (the well-tie ring) having an outer periphery 20 and a plurality of dissecting portions 22-25 that extend across the interior of the well-tie ring 90 to divide the ESD protection circuit into a plurality of segments 31-35. As specifically shown in segments 33 and 34, each one of the segments 31-35 includes a portion of the plurality of MOSFET transistors making up the ESD protection circuit. Each segments' set of transistors has corresponding source, drain, and channel regions within an active region 50 that is separated from the well-tie 21 by the dielectric region 11, which can be a Shallow Trench Isolation region (STI region).
One of the mechanisms that is useful in such a MOSFET configuration during an ESD event uses a bipolar device that is inherently present in the layout of the MOSFET, wherein such a bipolar device is a bipolar junction transistor (BJT) that can be turned on by a mechanism commonly referenced as “snapback” to provide additional protection during an ESD event. A schematic representation of such a bipolar device 60 is illustrated in FIG. 2, which illustrates a cross-sectional layout view along the lateral cross-section indicator line 2 of FIG. 1. In particular, the base of the inherent BJT 60, which is an NPN transistor, corresponds to the body of the MOSFET fingers, the collector of the BJT 60 corresponds to the drain regions of the MOSFET fingers, and the emitter of the BJT 60 corresponds to the source regions of the MOSFET fingers.
During an overstress event, snapback occurs due to a large voltage between the drain and the source of a MOSFET transistor of the ESD circuit that causes a change in a potential of the transistor's body region that causes the source-body junction diode of the MOSFET to turn on. The potential change in the body region can, for example, be due to drain-body junction leakage current during an ESD event that causes the body voltage to rise due to a voltage drop along a resistive path from the body region of the MOSFET near the MOSFETs source to a body tie. Once the source-body diode is turned on, current starts flowing between the drain and the source due to the inherent BJT device with the drain as the collector. The large collector current can cause impact ionization current that adds to the already flowing drain-body junction leakage current, further turning on the bipolar device. This can ultimately result in snapback, which is a characterized by a significant increase in the current that is provided between the source and drain and which typically causes the drain-source voltage to drop or “snap back” in a corresponding I-V chart. Much of the current flowing from the drain to the source is flowing down in the well region that is below the MOSFET channel. This snapback event can be relied upon to provide protection by sinking current when there is an ESD event, so long as the amount of snapback current at each segments' inherent bipolar device is low enough to be non-destructive to the MOSFET features during its duration.
However, the segment that first enters the snapback regime before other segments can be physically damaged if it has to sink the ESD current for a sufficiently long period of time before its ESD current load is reduced by other segments of the ESD protection circuit experiencing snapback. Furthermore, when the first segment enters the snapback regime, the drain-source voltage of the entire MOSFET typically drops due to the sudden reduction in the effective on-resistance of the first segment. This makes it less likely for other segments to enter the snapback regime as well because snapback is initiated by a large drain-source voltage. It is therefore desirable to increase the number of MOSFET segments that enter the snapback regime in order to maximize the failure current level of the ESD protection structure. Various proposals have been forwarded to facilitate more readily placing a greater number of segments of an ESD circuit into snapback during an ESD event, based on one of the segments which enters snapback first. For example, according to one proposal, a well-tie near a particular segment of an N-channel MOSFET is connected to one or more dedicated source regions of another segment. These dedicated source regions of the other segment are not connected to ground. Therefore, their voltage level gets elevated when the second segment enters bipolar conduction (snapback) due to the parasitic lateral BJT providing a current path from drain regions to the dedicated source regions. This may provide a feedback path that actively drives the well region at the well-tie in the particular segment to a higher voltage to facilitate snapback at the particular segment. This, and other techniques, however, add additional complexity to the ESD circuitry, and can reduce the number of transistor fingers that would otherwise be available to sink current during an ESD event. Furthermore, such well ties are not connected to a fixed voltage terminal (e.g. ground) and do therefore not aid in improving the latch-up robustness of the protection structure. Accordingly there is a need to provide further improvement in achieving snapback in inherent BJTs to provide protection during overstress events.